1. Field of the Invention
The present invention relates to serial data communication, and, in particular, to serial data communications using parity bit schemes.
2. Description of the Related Art
In serial data communication, there is a need for providing embedded clock signals, sometimes referred to as AC (alternating current) transitions. An encoder typically serializes data bits for serial transmission to a receiver having a decoder. By recognizing occasional AC transitions between binary 0s and 1s in the received serial bitstream, the decoder can synchronize its clock so that it samples the received bitstream properly. These AC transitions should occur frequently enough so that the decoder can synchronize properly, i.e. so that the encoder's clock signal is sufficiently embedded in the serial bitstream.
To ensure that a long run of 0s or 1s does not occur that would cause the decoder to become unsynchronized, the encoder should ensure that enough AC transitions occur often enough in the serial bitstream so that the decoder can detect the clock signal at which the bitstream is encoded and accurately sample and decode the serial bitstream data. One solution is to insert a special transition bit every n bits, e.g. every 10th bit, which is the inverse of the preceding bit, to ensure that there are always AC transitions often enough to embed the clock signal. Unfortunately, this technique is inefficient since 1/n of the bitstream is used to provide a clock signal rather than information. There is, therefore, a need for improved methods for providing for AC transitions in serial bitstreams. There is also a need to make efficient use of the available bandwidth to transmit information.